ATA8743-PXQW【PDF 21/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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Sheet目录52

17页 18页 19页 20页 [21页]22页 23页 24页 25页

9152BINDCO02/10

ATA8743

9.3

Pin Descriptions

9.3.1

VCC

Supply voltage.

9.3.2

GND

Ground.

9.3.3

Port B (PB3...PB0)

Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability except PB3 which has the RESET

capability. To use pin PB3 as an I/O pin, instead of

RESET pin, program (0) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low

will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny24/44/84 as listed on

Section 19.3 Alternate Port Functions on page 77.

9.3.4

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in Figure 16-1 on page

56. Shorter pulses are not guaranteed to generate a reset.

9.3.5

Port A (PA7...PA0)

Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port A has an alternate functions as analog inputs for the ADC, analog comparator, timer/coun-

ter, SPI and pin change interrupt as described in Alternate Port Functions on page 77

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